SystemVerilog `fork...join`

🧵 SystemVerilog fork...join – Parallel Execution Explained

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In SystemVerilog, the fork...join construct allows you to execute multiple statements or processes in parallel, similar to threads in software programming. This is especially useful in testbenches, stimulus generation, and concurrent checks.

🔧 Basic Syntax

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fork
  statement_1;
  statement_2;
  statement_3;
join

• All the statements inside fork...join start executing simultaneously
• The simulation waits for all of them to complete before moving to the next statement after the join

📌 Variants of join

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Example with join:

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fork
  #10 $display("A");
  #5  $display("B");
join
$display("All done");  // Executes after both A and B

Example with join_any:

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fork
  #20 $display("Slow task");
  #5  $display("Fast task");
join_any
$display("One of them finished");  // Executes after first task completes

Example with join_none:

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fork
  #10 $display("Running...");
  #20 $display("Still running...");
join_none
$display("No wait, move on immediately");

🔁 disable fork

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SystemVerilog allows you to terminate all child processes started within a fork...join block using disable fork;.

initial begin
  fork
    forever begin
      #1 $display("Looping forever...");
    end
    #10 disable fork;  // Stop the forever loop after 10 time units
  join
end

🚨 Synthesis Warning

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• fork...join is not synthesizable
• It is intended for testbenches and behavioral modeling only
• Do not use in RTL code

🧪 Typical Use Cases

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• Launching parallel stimulus in testbenches

• Waiting for multiple monitors or checks

• Running concurrent tasks like:

  • packet send + scoreboard check
  • stimulus + timeout monitor

• Creating timeouts or watchdogs with join_any

✅ Best Practices

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• Use join when all parallel threads must complete
• Use join_any for timeouts or race conditions
• Use join_none to launch background tasks
• Use disable fork to gracefully abort all threads

🧠 Summary Table

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The fork...join family in SystemVerilog enables powerful concurrent behaviors, especially in UVM and testbench environments. Understanding and using it correctly makes your simulations more realistic, modular, and controlled.