Table of Contents

🧠 What is Verilator?
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Verilator is an open-source simulator that converts Verilog HDL (Hardware Description Language) code into high-performance C++ or SystemC code. It is primarily used for hardware modeling and verification. Unlike other HDL simulators, Verilator is designed for cycle-accurate, synthesizable Verilog code.

🔑 Key Features of Verilator
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Translates Verilog into high-speed C++/SystemC models.
Offers excellent performance for large-scale designs.
Open source under the GNU GPL license.
Supports waveform generation and debugging.
Suitable for FPGA and ASIC development flows.

🛠️ Verilator Installation Guide
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There are several ways to install Verilator: prebuilt packages, source build, or package managers.

🐧 1. Installing on WSL (Ubuntu) or Native Linux
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Step 1: Install Required Dependencies
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Run the following in your terminal:

sudo apt update
sudo apt install git make autoconf g++ flex bison libfl2 libfl-dev zlib1g zlib1g-dev

Step 2: Clone Verilator Source Code
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git clone https://github.com/verilator/verilator.git
cd verilator

Step 3: Checkout Stable Version & Build
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git checkout stable

🛑 If you encounter an error related to help2man, it’s because the utility used for generating man pages is missing.

Fix: Install `help2man`
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sudo apt install help2man -y

Step 4: Build and Install
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autoconf
./configure
make -j$(nproc)
sudo make install

Step 5: Verify Installation
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verilator --version

🪟 2. Installing on Windows (via WSL)
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Install WSL and a Linux distribution (e.g., Ubuntu). WSL Setup Guide
Open the WSL terminal and follow the Linux installation steps above.

🍏 3. Installing on macOS
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Using Homebrew
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brew update
brew install verilator
verilator --version

💻 4. Installing on Native Windows
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Verilator cannot run natively on Windows without a Linux-like environment. Use:

WSL
Cygwin
Virtual Machine
Docker

🚀 Verilator Usage Example
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Step 1: Create a Verilog Design
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// hello.v
module hello(input logic clk, output logic led);
    always @(posedge clk) led <= ~led;
endmodule

Step 2: Simulate with Verilator
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1. Generate C++ Model
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verilator --cc hello.v --exe sim_main.cpp

2. Compile the Model
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make -j -C obj_dir -f Vhello.mk Vhello

3. Run Simulation
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./obj_dir/Vhello

Step 3: Generate Waveform (Optional)
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Use the --trace flag to enable VCD waveform dumping:

verilator --cc hello.v --exe sim_main.cpp --trace

🧩 Useful Verilator Commands
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Command	Description
`verilator --version`	Shows the installed Verilator version.
`verilator --lint-only file.v`	Lints Verilog file for syntax/warnings.
`verilator --trace`	Enables waveform tracing during simulation.
`verilator --cc file.v`	Translates Verilog to C++ code.

❓ Frequently Asked Questions
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1. Does Verilator support only synthesizable Verilog?
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Yes. Verilator is limited to synthesizable, cycle-accurate Verilog. It does not support event-driven simulation or non-synthesizable testbenches.

2. Why is Verilator so fast?
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Verilator converts Verilog to native C++/SystemC code, which is then compiled and run as a software application—much faster than traditional interpreted simulators.

If you need further help or want a walkthrough for integrating with testbenches, waveform viewers (GTKWave), or CMake setups, feel free to ask! 😊